1. Field of the Invention
The present invention relates to a semiconductor memory device such as a read-only memory equipped with a redundant circuit.
2. Description of the Related Art
Recently, as the operation of the microprocessor has become faster, faster-operating semiconductor memory devices have been strongly demanded. A semiconductor memory device realizing faster usual random access and further having a high-speed readout mode, referred to as the "page mode", "burst mode", "serial mode", etc., with respect to continuous addresses, is now being developed, as described in, for example, Japanese Laid-open Publication No. 8-63990, which corresponds to U.S. Pat. No. 5,619,473.
For example, in the page-mode readout operation, a plurality of memory cells in a memory cell array are simultaneously selected in accordance with a column address and a row address of an input address, and a plurality of data are read out from the selected plurality of memory cells to a sense amplifier as page data. The addresses in the page are then changed under this condition, whereby the data of the selected plurality of memory cells are successively output at a high speed.
Referring to FIG. 9, a read-only memory (hereinafter, referred to as a "ROM") having a page-mode function will be described.
A ROM 200 has 16 Mbits of storage capacity. In the ROM 200, column addresses A0 to A6 and row addresses A7 to A19 are input, and 16-bit data D0 to D15 are output. One page includes four (4) words (i.e., 16 bits.times.4).
Pages are specified by the addresses A2 to A19, and word data in each page is accessed by the addresses A0 and A1. Hereinafter, for clarity, the addresses A0 and A1 will be referred to as "intra-page addresses", and the addresses A2 to A19 will be referred to as "page addresses".
Furthermore, the ROM 200 is equipped with memory cell arrays MA0 to MA15 in which memory cells are arranged in a matrix, and bit data corresponding to each bit of 16-bit output data D0 to D15 is stored in each memory cell array.
The ROM 200 further includes address buffers AB7 to AB19, a pre-row decoder PRD, and a row decoder XDEC, as a row selection unit for selecting memory cells in the rows corresponding to the row addresses A7 to A19. The ROM 200 also includes address buffers AB2 to AB6, a pre-column decoder PCD, and column decoders YDEC, as a column selection unit for selecting memory cells in the columns corresponding to the column addresses A2 to A6.
The column decoders YDEC are provided for the respective memory cell arrays MA0 to MA15 so as to simultaneously select four (4) columns of bit lines in accordance with the addresses A2 to A6. In the subsequent stage of each column decoder YDEC, four sense amplifiers SA0 to SA3 are provided, which detect and amplify bit signals forming one page appearing in selected four bit lines in a parallel manner.
Furthermore, the ROM 200 includes address buffers AB0 and AB1, a page mode decoder PMD, and a selector SEL, as a word data selection unit for selecting the word data corresponding to the intra-page addresses A0 and A1. The selector SEL alternatively selects outputs DOS0 to DOS3 of the sense amplifiers SA0 to SA3 in response to signals P0 to P3 from the page mode decoder PMD. Furthermore, in the subsequent stage of the selector SEL, an output circuit OB is provided for generating the output from either one of the selected sense amplifiers as output data D0 (to D15).
In the memory cell arrays MA0 to MA15 of the ROM 200, bit lines are arranged hierarchically, as shown in FIG. 10. More specifically, in FIG. 10, sub-bit lines (e.g., SB0, SB1) of the respective memory cell arrays are connected to sources and drains of a set of adjacent memory cells, whereby a predetermined plurality of memory cells in the identical column are commonly connected.
Furthermore, main bit lines (e.g., MB0, MB1) are connected to the sub-bit lines (SB0, SB1) through selection transistors (TB0, TB1) and arranged in the memory cell array so as to be orthogonal to word lines. Gates of the selection transistors (TB0, TB1) are connected to selection signal lines (BS0, BS1) arranged in parallel with the word lines so as to select the sub-bit lines (SB0, SB1).
Furthermore, as shown in FIG. 10, the column decoder YDEC includes 128 column selection MOS transistors, with 32 column selection MOS transistors TG0 to TG31 being one unit. One end of the column decoder YDEC is connected to each bit line of the memory cell array, and the other end is commonly connected to the sense amplifiers SA0 to SA3. When one of column selection signals CS0 to CS31 becomes active, four out of 128 column selection MOS transistors are brought into conduction, whereby four out of 128 bit lines of the memory cell array are simultaneously selected. As a result, data DOB0 to DOB3 from four memory cells of each memory cell array simultaneously appear in the outputs of the column decoder YDEC. The sum of the outputs of 16 column decoders of each memory cell array corresponds to one page of data.
Next, a page-mode operation of a circuit shown in FIGS. 9 and 10 will be described with reference to a timing diagram shown in FIG. 11.
First, when the addresses A0 to A19 are determined at time t0, the first word of data of a page P.sub.h specified by the page addresses A2 to A19 is read out. Such a readout of the first data is usually conducted in the same way as in a random access mode as described below.
When the row addresses A7 to A19 are determined at time t0, one word line passing through the memory cell arrays MA0 to MA15 is activated (become high-level) by the above-mentioned row selection unit. On the other hand, when the column addresses A2 to A6 are determined at time t0, either one of the column selection signals CS0 to CS31 is activated by the above-mentioned column selection unit. Then, four column selection MOS transistors in the column decoder YDEC, which have received the activated column selection signals, are simultaneously turned on, whereby four bit lines connected to these column selection MOS transistors are selected.
Next, data signals of four memory cells positioned at crossed points of four selected bit lines and one activated word line are respectively input to the sense amplifiers SA0 to SA3 through the column decoder YDEC, and the outputs DOS0 to DOS3 of the respective sense amplifiers SA0 to SA3 are determined at time t1. Thus, one page of word data specified by the page addresses A2 to A19 is prepared.
Then, one of the signals P0 to P3 from the page mode decoder PMD becomes active in accordance with the intra-page addresses A0 and A1. One of the outputs DOS0 to DOS3 of the sense amplifiers is thus selected by the selector SEL, and the first word data W0 (D0 to D15) of the page P.sub.h is output at time t2. When the intra-page addresses A0 and A1 are changed at time t3, the selector SEL changes its selection of the sense amplifier outputs, and an output circuit OB outputs a second word W1 of the page P.sub.h at time t4. Thereafter, the intra-page addresses A0 and A1 are successively changed in a similar manner, and the third word W2 and the fourth word W3 are successively output.
Next, in the case where the page addresses A2 to A19 are changed and the subsequent page P.sub.h+1 is accessed, only the first word of the page P.sub.h+1 is accessed in the same way as in a random access mode. Thereafter, other words of the page P.sub.h+1 are read out at a high speed in accordance with the intra-page addresses A0 and A1. In the case of reading out the second word W1 to the fourth word W3, the selector SEL selects and outputs data DOB1 to DOB3 which have been previously read out at the same time as the readout of the first word and prepared for the outputs of the sense amplifiers SA1 to SA3. Therefore, compared with a random access in which a weak data signal is read out and output from a memory cell at each access, output data can be determined in a short period of time, making it possible to read out data at a high speed.
Hereinafter, a typical conventional replacement operation (in other words, a compensation operation) for a defective bit will be explained.
As disclosed, for example, in Japanese Laid-open Publication No. 6-76591, which corresponds to U.S. Pat. No. 5,452,258, in order to improve the production yield of a ROM such as a mask ROM, there is provided a ROM equipped with a redundant circuit for compensating for a defective bit. FIG. 12 is a block diagram for illustrating the exemplary configuration of such a ROM.
A ROM 200A in FIG. 12 includes a redundant circuit RDN which compensates for a defective bit contained in the data read out from a memory array.
The redundant circuit RDN includes: a detecting unit (or a replacement bank address storage portion) A for storing an address at which a defective bit is present and detecting an access to such a stored address; a replacement bit storage portion C for storing output bit position information of the defective bit and outputting such a stored information based on the detection result of the replacement bank address storage portion A; and, a replacement cell data storage portion B for storing a replacement data and outputting the stored replacement data based on the detection result.
Hereinafter, the replacement of a defective bit with the redundant circuit RDN will be described.
First, an address at which a detective bit is present and a bit position of the defective bit in the output data D0 to D15 (or output bit position information) are previously determined, for example, by a probing test using a memory tester. During the data readout operation, when the replacement bank address storage portion A detects a defective address, the replacement bit storage portion C and the replacement cell data storage portion B output, respectively, the output bit position information RD0 to RD15 and the replacement data RDAT.
On the other hand, data read out from a memory cell array specified by the defective address is detected and amplified by a sense amplifier AMP to be given to a switch ST. The switch ST selects the replacement data RDAT from the replacement cell data storage portion B and outputs it as the output data D0 (to D15) through the output circuit OB, based on the output bit position information RD0 to RD15 from the replacement bit storage portion C. Thus, the data from the defective bit is replaced with the replacement data, thereby compensating for the defect.
In a memory cell array including the above-mentioned hierarchically arranged bit lines, if one defective bit exists, data is prevented from being read out from the other memory cells connected to the same sub-bit line together with the defective bit. Therefore, replacement is conducted on the basis of a memory cell group (hereinafter, referred to as a "bank", i.e., a group of memory cells surrounded by a broken line in FIG. 12) connected to the same sub-bit line, whereby a redundant circuit can be efficiently constructed. In the example shown in FIG. 12, the bank is specified by the column addresses A0 to A6 and the row addresses A11 to A19 (hereinafter, referred to as a "bank address").
Hereinafter, a method for compensating for a defect in a mask ROM including hierarchically arranged memory cell arrays MA0 to MA15 composed of the above-mentioned banks will be briefly described.
First, a bank address, at which a defective bit is present, and output bit position information are previously specified, for example, by a probing test using a memory tester. The bank address at which the defective bit is present is stored in the replacement bank address storage portion A, the output bit position information of the defective bit is stored in the replacement bit storage portion C, and the replacement data of the bank is stored in the replacement cell data storage portion B, whereby the redundant circuit RDN is programmed.
In the case where the redundant circuit RDN is programmed as described above, when a supplied address matches the bank address stored in the replacement bank address storage portion A, a replacement data RDAT of a memory cell corresponding to a word line which becomes active is read out of the replacement cell data storage portion B. Thus, bit data MDAT0 to MDAT15 from the memory cell array specified by the output bit position information RD0 to RD15 from the replacement bit storage portion C are replaced with the replacement data RDAT.
In the above explanation, the mask ROM having a NOR-type cell array structure has been described. Alternatively, the similar replacement can be conducted even in the mask ROM having an NAND-type cell array structure on the basis of a series of memory cell groups.
However, in the case where a defective bit is compensated for in the above-mentioned conventional semiconductor memory device, the time required for a series of operations of the redundant circuit RDN tends to become long, and the readout time of the replacement data becomes longer than the access time in a page-mode. Therefore, when the redundant circuit RDN is operated in a page mode, the access time in a page-mode becomes longer.
Furthermore, in the case where a defective bit is compensated for by operating the redundant circuit RDN only when a page is changed (at this time, the access time becomes longer as in the usual random access) for the purpose of avoiding adverse influences of the operation of the redundant circuit RDN, all the words contained in one page will have to be replaced. This remarkably increases the size of the redundant circuit, and makes it difficult to replace many bits, resulting in making it difficult to effectively perform the replacement operation.